Various signal processing applications require the use of a multiphase clock in which clock signals are uniformly distributed in phase. FIG. 1 illustrates an example of the use of such a clock in a Clock Data Recovery (CDR) circuit. Contained in the overall CDR circuitry are essentially two loops, a first loop 130 in which phase locking to data occurs and a second loop 140 in which a multiphase clock is used to provide proper alignment of clock phases between 0° and 360°.
As depicted in FIG. 1, a reference clock signal 110 is supplied to a Voltage Controlled Delay Loop (VCDL) component 120. An internally available clock, derived from the reference clock 110, is used by a data sampling component 160 to oversample incoming data 150. Based on the results of this oversampled data, the internal clock is delayed so that it provides data sampling adjusted to the center of the “eye” pattern of the received serial data 150. FIG. 2 illustrates an example of sampling of a received digital data signal wherein S0 and S1 depict sampling times corresponding to the center of the eye pattern. Times T0 and T1, are transition points which are used by the system to determine these proper sampling times. In a VCDL system, phase of the sampling clock is constantly adjusted to keep up with phase deviations of incoming data.
One well-known problem in the prior art is the timing variations that occur within the second loop 140 itself that must be properly resolved before accurate data sampling is attained. There exist two components of these timing variations:
1. Static Variations:                Static variations are due to static phase offsets resulting from clock edge placement errors. These errors are caused by fixed error sources such as (a) semiconductor device fabrication variations, (b) circuit mismatches and (c) layout asymmetries.        
2. Dynamic Variations:                The dynamic variations are due to deterministic jitter, random jitter, or periodic jitter.        
Static variations are due to physical mismatches. Such variations are a significant source of timing errors that are conventionally addressed with a calibration process. The position of the clock edges are measured with averaged phase timing measurements using histogram counters. The resulting histogram of these count values indicates the variation of the clock phases. The mitigation of these variations, or clock phase trimming, is performed by equalizing the histogram count values. In particular, this mitigation is typically performed by tuning adjustable tail currents within the clock buffers.
One example of such a histogram technique is described in a November 2001 Stanford dissertation thesis entitled “PRECISION CMOS RECEIVERS FOR VLSI TESTING APPLICATIONS” by Daniel K. Weinlader, said thesis hereby incorporated by reference in its entirety. In Weinlader's process, as in other conventional techniques, the trimming process has to be performed in real time and accordingly, the following components are typically required:                (a) a controlled ppm (part per million) generator,        (b) a high speed phase comparator,        (c) a high speed counter and        (d) complex histogram processor.As a result, this solution is expensive and can not be practically implemented in many commercial products.        